The paper “A 24-GHz CMOS Power Amplifier with Dynamic Feedback and Adaptive Bias Controls” by Yoonsoo Jin and Songcheol Hong demonstrates a millimeter-wave power amplifier for 5G using 65-nm bulk CMOS. Two techniques—Dynamic Feedback Control (DFC) and Adaptive Bias Control (ADB)—jointly improve linearity, gain, and efficiency around 24 GHz.
Overview
The work targets the 24 GHz 5G band, where nonlinearity and efficiency loss traditionally limit CMOS PAs. The proposed amplifier integrates:
- DFC: dynamically adjusts feedback based on the input envelope to flatten gain and reduce IMD3.
- ADB: adaptively controls the gate bias of common-source devices with input power, boosting power gain, saturation power, and PAE while preserving linearity.
Key Contributions & Innovations
1) Dynamic Feedback Control (DFC)
DFC varies the feedback resistivity using a cold-FET driven by the input envelope. This improves both AM-AM and AM-PM characteristics and suppresses third-order intermodulation, which is critical for wideband, high-order 5G modulation.
2) Adaptive Bias Control (ADB)
ADB raises the CS gate bias with input power, yielding higher gain, Psat, and peak PAE. The authors employ a restricted-bias inverter for process robustness, stabilizing operation across PVT variations and preventing device over-stress—important for reliable mmWave CMOS.
Measured Performance — 24 GHz
- Saturation Power (Psat): 18.7 dBm
- Gain: 15.3 dB
- Peak PAE: 37.2%
- Linear Output Power: 12.9 dBm with linear PAE of 14.8%
CW and two-tone measurements align with simulations, indicating robust linearization from the combined DFC + ADB approach.
Research Gap Addressed
Prior mmWave CMOS PAs struggled to maintain linearity/efficiency due to intrinsic device nonlinearity and low breakdown voltage. Earlier fixes (e.g., neutralization, harmonic termination) were sensitive to process spread. This paper closes that gap with envelope-aware feedback (DFC) and input-tracked biasing (ADB) that are stable at high frequency and suitable for 65-nm commercial integration.
Challenges & Future Directions
- Voltage headroom: Low CMOS breakdown necessitates cascodes; still limits ultimate output power and efficiency.
- Generalization: DFC/ADB parameters may need retuning beyond 24 GHz or for different PA cores.
- Productization: Mass-production requires further optimization for cost, calibration, and reliability.
Conclusion
By combining Dynamic Feedback Control with Adaptive Bias Control, the authors deliver a 5G-ready 24-GHz CMOS PA with improved linearity, gain, and efficiency. The measured results validate the approach and point to promising extensions in hybrid architectures and even higher-frequency bands for future wireless systems.
