VLSI Design Verification

This course provides an end-to-end understanding of VLSI Verification — starting from digital design fundamentals and progressing to advanced SystemVerilog, UVM methodologies, formal verification, power-aware verification, and emulation techniques.
Through hands-on labs, mini-projects, and a capstone, learners will develop the skills required for RTL-to-SoC level verification in modern semiconductor workflows.

Learning Outcomes

By the end of this course, learners will be able to:

• Understand digital design and HDL basics relevant to verification.
• Build System Verilog-based CRV and assertion-driven test benches.
• Apply UVM methodology for scalable and reusable verification environments.
• Perform coverage analysis, gate-level simulation, and regression.
• Work with protocols, processor-based verification, and low-power verification flows.
• Use formal verification, emulation, and CI/CD pipelines for sign-off.
• Deliver industry-grade verification reports with coverage and assertion results.

Course Structure & Modules

Module 1: Digital Design Fundamentals

• Number Systems & Boolean Algebra
• Combinational & Sequential Circuits
• Setup/Hold, Clock Skew, Metastability
• FSM Design Principles
  Assignment: FSM for Traffic Light or Vending Machine

Module 2: Verilog HDL and Test Benches

• Verilog Modules, Ports, and Continuous Assignments
• Blocking vs Non-Blocking Assignments; Always Blocks
• Writing Basic Test Benches
• Limitations of Traditional Verilog Test Benches
• Hierarchical Design & Code Reusability
  Lab: FSM / MUX / Counter in Verilog

Module 3: Fundamentals of Verification

• Verification Levels: IP, Subsystem, SoC, System
• Test Planning & Test Case Writing
• Introduction to Assertions and Their Necessity
• Coverage Types: Functional & Code Coverage
  Activity: Create Test Plan for FIFO Verification

Module 4: SystemVerilog Basics for CRV

• SystemVerilog Data Types: logic, bit, int, arrays
• Object-Oriented Programming (OOP) in SV: Inheritance, Encapsulation
• Constructors & Randomization Concepts
• Program Block and its Usage in Test Benches
  Mini Project: Random Stimulus Generator for ALU

Module 5: Constrained Random Verification (CRV)

• Architecture & Advantages of CRV
• Developing Reusable Random Test Benches
• Writing Constraints & Coverage Strategies
• Seeding & Debugging Random Failures
  Exercise: Randomized ALU/Counter Testbench

Module 6: Assertions in SystemVerilog

• Immediate vs Concurrent Assertions
• Sequences, Properties, Temporal Expressions
• Protocol Assertion Examples: Ready/Valid, Handshake
  Lab: SVA for FIFO / Handshake Protocol

Module 7: Testbench Architecture & Transaction Modeling

• Testbench Components: Driver, Monitor, Scoreboard, Generator
• Virtual Interfaces & Clocking Blocks
• Transaction-Level Modeling (TLM) Concepts
  Lab: Build Testbench for FIFO Verification

Module 8: UVM Fundamentals

• UVM Base Classes & Simulation Phases
• UVM Components: Sequence, Sequencer, Agent, Environment, Monitor, Driver
• Factory Pattern, Config DB, and Objection Mechanism
  Lab: UVM Testbench for UART or APB Slave

Module 9: UVM Advanced Concepts

• UVM Messaging & Debug Utilities
• Phase Jumping, TLM FIFO, Callbacks
• Integrating Scoreboarding & Coverage
• Just-In-Time (JIT) Sequences
  Lab: UVM Scoreboard for SPI Protocol

Module 10: Protocol & Processor-Based Verification

• AMBA Protocols: AXI, AHB
• Peripheral Protocols: UART, SPI
• Introduction to Embedded C for Verification
• Types of Processors: ARM, RISC-V, etc.
• Processor-Based Test Benches
• C-UVM Communication
  Activity: Develop UVM-C Interface Testbench

Module 11: Functional & Code Coverage

• Writing Covergroups, Coverpoints, and Bins
• Cross Coverage and Sampling Techniques
• Writing Coverage in SV Classes
• Code Coverage Types: Line, Toggle, FSM
  Exercise: Coverage Plan & Report for ALU/FIFO

Module 12: Gate-Level Simulation & Regression

• Need for GLS and Setup Procedure
• SDF Back-Annotation
• Running & Debugging GLS
• Regression Basics & Log Automation
  Activity: Shell/Python Scripts for Automated Regression

Module 13: Power-Aware Verification

• UPF Introduction & Low-Power Design Flows
• Dynamic Power Gating and State Retention
• Integrating Power Models into Simulation
• Assertion-Based Power Checks
  Lab: Power-Aware Simulation Setup

Module 14: Formal Verification

• Introduction to Formal Verification Techniques
• Equivalence Checking vs Property Checking
• Common Formal Tools: JasperGold, VC Formal
• Formal Use Cases in RTL & Protocol Verification
  Activity: Formal Check for FSM or Protocol

Module 15: Emulation & Performance Verification

• Why Emulation is Needed
• Hardware Emulators: Palladium, Veloce, Zebu
• Acceleration Techniques & Co-Simulation
• Performance Metrics and Bottleneck Analysis
  Workshop: Emulation Flow Overview

Module 16: Tools & Capstone Project

• Git for Version Control in Verification Projects
• Shell, Python, and TCL Scripting for Automation
  Capstone Project: Verify a UART/SPI/Timer IP using UVM + Coverage + Assertions + Report Generation.
  Deliverables: Verified IP, Coverage Report, Assertion Log, Project Review Document

Suggested Industry Additions (Optional Modules)

Module 17: Functional Safety & Security Verification

• ISO 26262 & DO-254 Basics
• Fault Injection Methodologies
• Safety Mechanism Coverage
• Security Checks for Data Path & Boot

Module 18: CDC/RDC Verification

• Understanding Asynchronous Domain Crossings
• Tools & Methodologies
• CDC/RDC Checks with Example RTL

Module 19: Portable Stimulus Standard (PSS)

• Introduction to PSS
• Scenario-Based Verification Concepts
• PSS with UVM Integration

Module 20: CI/CD for Verification

• Jenkins/GitLab CI Basics
• Automated UVM Regression Pipeline
• Email & Dashboard Integration for Reports