Circuits to Thinking : Analog Mind by Behzad Razavi

Inspired by Behzad Razavi’s IEEE SSCS Magazine column, “The Analog Mind.” This synthesis distills recurring methods, design trade-offs, and reusable checklists across multiple installments, with links to the full papers for deeper study.

From Circuits to Thinking: What “Analog Mind” Actually Models

Rather than showcasing isolated schematics, Razavi consistently teaches a reproducible design workflow. Consequently, you can lift the method directly into tape-out-bound projects:

Begin with system numbers—bandwidth, noise/jitter, headroom, power—and only then map to an architecture whose physics can actually close in your process and supply. The TIA and phase-interpolator pieces both start with concrete targets, then back-solve topology, biasing, and sizing. UCLA Sea
Quantify trade-offs instead of hand-waving them. For instance, in LDOs the zeros/poles that deliver phase margin across load also set PSRR in the band your consumer cares about; in broadband I/O, return-loss and peaking are negotiated, not assumed. UCLA Sea
Exploit native device strengths. In low-VDD CMOS, the humble inverter becomes a versatile, PVT-tolerant primitive (buffers, latches, oscillators, pumps, and even quasi-analog roles) when sized and loaded intelligently. UCLA Sea

Reusable Patterns and “Sanity Anchors”

Spec Tables that Drive Everything

First and foremost, write the spec table before schematics. The TIA article, for example, targets ≈28 GHz BW for 40 Gb/s NRZ (≈0.7·Rb) while bounding input-referred noise and power; every design decision points back to those anchors. Likewise, the PI column pins operation near 28 GHz with ≈0.4 ps step resolution and ≈1.1 ps_rms jitter and then derives interpolation and buffering. UCLA Sea

Compensation Where It Actually Matters

Next, recognize that who you feed determines compensation. The load’s impedance/ESR dictates where zeros/poles must land for stable phase margin and for PSRR in the band that matters to the consumer (e.g., a VCO rail). Therefore, treat AC and transient behavior as one loop-shaping problem. UCLA Sea

Parasitics as First-Class Citizens

Moreover, the TIA piece elevates pad + PD capacitance from nuisance to hard constraint. You size g_m, pick feedback, and place the dominant pole around those parasitics—not around idealized nodes that won’t exist in silicon. UCLA Sea

“Inverter-First” Thinking

Finally, when headroom is scarce, inverter-centric constructs deliver compact, robust solutions. The series catalogs dozens of roles in modern nodes and quantifies performance so you can pattern-match quickly during synthesis. UCLA Sea

Portable Case Studies You Can Drop into Your Flow

Transimpedance Amplifier (≈40 Gb/s NRZ)

Core lesson: BW and input noise are set by external C (pad + photodiode), not by optimistic loop algebra. Consequently, you select Z_T, budget current-noise density, set g_m and feedback for ≈28 GHz, and verify across SS/low-VDD corners. Reproduce the method, not just the numbers.

Do this: Sweep pad capacitance in PEX; plot input-referred current noise vs. 3 dB BW—you’ll hit the same trade-off wall the article quantifies. UCLA Sea

Phase Interpolator (~28 GHz, ~0.4 ps Steps)

Core lesson: Treat resolution and jitter as budgeted specs that drive device sizing, segmentation, and buffer isolation before clever circuits. Consequently, the spec-to-architecture progression becomes a clean template for CDR PIs or LO grids.

Do this: Build a spreadsheet mapping time-step targets to effective phase resolution vs. buffer delay spread; then size interpolation weights and post-buffers and validate with PEX skew distributions. UCLA Sea

LDO for Mixed-Signal Islands

Core lesson: Pick compensation to the consumer (VCO, ADC), not to a generic load. Co-optimize PSRR in the required band while preserving phase margin across load steps and VDD droops—one loop, one solution.

Do this: For a VCO-fed LDO, derive a PSRR mask from the VCO’s K_VCO·S_VDD and phase-noise target; then place zeros to cover that band while still meeting transient specs at the worst-case load. UCLA Sea

Biquadratic Filters (SC and CT)

Core lesson: Non-ideal R_on, finite op-amp gain/BW, and switch timing skew reshape poles/zeros. Therefore, design for the effective biquad (not the textbook one) and plan tuning to retain rejection. UCLA Sea

“Fifty Applications of the CMOS Inverter” (Parts 1–4)

Core lesson: In deeply scaled CMOS, the inverter is a power-efficient workhorse—from sense amps and latches to oscillators and charge pumps—when you treat it as a sized, load-aware primitive with predictable PVT behavior. Use the series as a rapid pattern library. UCLA Sea, UCLA Sea

A Compact Review/Bring-Up Checklist

Spec-first: Slide 1 is the table—BW, PN/jitter, noise, swing, headroom, power, area. Tie each choice back to it. UCLA Sea
Corner-honest: Simulate SS/low-VDD/high-T for the rails you’ll have in system, not bench-top ideals. The column examples close under harsh corners. UCLA Sea
Parasitic-aware: Include pad/package/PD caps, bondwires, and critical routing as budget terms early; do not wait for final PEX to learn first-order truths. UCLA Sea
One loop, one problem: In regulators and CDRs, AC and transient shaping are the same pole/zero placement exercise. UCLA Sea
Primitive-led: If an inverter (or another native primitive) solves it with fewer devices and better PVT behavior, prefer it. The series is proof by construction. UCLA Sea