Digital Interview Questions for VLSI
1. Digital Design Basics
- Number system conversions
- One’s, two’s complement, XS-3 code
- Binary to Gray and vice versa
- NAND and NOR as universal gates
- Implement gates using NAND/NOR
- SOP/POS to NAND/NOR implementation
- Full adder and subtractor concepts
- Look-ahead carry adder basics
- K-map and Tabulation minimization
- Boolean laws and theorems
2. Multiplexer and Decoder-Based Design
- Gates using 2:1 multiplexer
- Function implementation using 4:1, 8:1 Mux
- Concept of Mux tree
- 4:1 Mux using 2:1 Mux
- Full adder using two 4:1 Mux
- 16:1 Mux using 2:1 Mux
- 2:1 Mux using tri-state buffers
- Function implementation using 2:1 Mux
- Full adder using 3:8 decoder
- Priority encoder questions
3. Sequential Circuits
- Latch vs. Flip-Flop
- Flip-Flop conversions (JK ↔ SR, T ↔ D)
- SISO and PIPO design
- Cycles for Johnson, Ring, Ripple counters
- Up/Down and Decade counters
- Mod-n counter with duty cycle
- Sequence detector FSM (10101, etc.)
- Overlapping vs. Non-overlapping FSM
- Mealy vs. Moore machines
4. Timing and Performance
- Digital design hazards
- Setup vs. Hold time (with waveforms)
- Propagation vs. Contamination delay
- Clock skew, slack, slew concepts
5. Verilog/VHDL Section
- Blocking vs. Non-blocking
- Intra vs. Inter assignment delay
- Task vs. Function differences
- reg vs. wire
- Code-based output prediction
- Transport vs. Inertial delay
- Wait statements in VHDL
- Async vs. Sync D Flip-Flop code
- No latch inference in RTL
- RTL coding guidelines (Sunburst)
- Full-case vs. Parallel-case
- Task calling function possibility
- Register swap with/without temp variable
- $monitor vs. $strobe
- Verilog vs. VHDL
- if-else vs. case synthesis
- Case equality vs. inequality
- Stratified event queue
- signal vs. variable (VHDL)
- Delta delay in VHDL
- VHDL modeling styles
6. CMOS Section
- Latch-up
- Body effect
- Stick diagrams for gates
- NAND preferred over NOR
- DRC, LVS rules
- CMOS fabrication basics
- Electromigration
- Domino effect
- Subthreshold conduction
- Channel length modulation
- BJT vs. MOSFET
- Parasitic and diffusion capacitance
7. Miscellaneous Section
- ASIC vs. FPGA flow
- CLB, IOB, LUTs in FPGA
- FIFO design (sync/async)
- FIFO depth calculation
- Reset strategies
- Reset recovery time
- Memory controller design in Verilog
- Cache memory: hit/miss ratio
- Basic Linux commands
- System Verilog fundamentals
- Synthesizable constructs (Verilog, VHDL)
- Computer architecture basics
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