DFT Books For VLSI Engineers
A brand-aligned, expert reading map—spanning ATPG theory and X-tolerance to compression, LBIST/MBIST, IJTAG/1500, and hierarchical SoC test architectures.
If terms like path-delay ATPG, on-chip clock control, scan compression, and hierarchical wrappers are already in your daily vocabulary, then this list is your next routing layer. Moreover, every title below is DFT-first—chosen for practical alignment with modern EDA/ATE flows and, furthermore, for depth where advanced teams actually struggle: volume, power, access, and diagnosis. Therefore, consider this your structured roadmap to elevate test quality without sacrificing power or schedule.
SEO focus: best DFT books for VLSI, Design for Testability books, DFT engineer books, scan design, ATPG, LBIST, MBIST, SoC DFT, test compression.
Core References (Read & Own)
1) Digital Systems Testing and Testable Design — Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman
Why it matters: the canonical algorithmic base—fault models, simulation, and ATPG (D-algorithm/PODEM/FAN).
Master with it: sequential ATPG, transition/path-delay, design transformations; additionally, use the theory to explain untestables, reconvergence, and constraint side-effects.
2) Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI — Michael L. Bushnell, Vishwani D. Agrawal
Why it matters: rigorous breadth across digital, LBIST/MBIST, boundary-scan, and mixed-signal touchpoints.
Master with it: quality economics, sequential pattern generation, BIST architectures; furthermore, learn the bridge from DFT rules to ATE realities.
3) VLSI Test Principles and Architectures: Design for Testability — Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen
Why it matters: a modern, architecture-centric deep dive, tightly aligned with commercial flows.
Master with it: scan cell/chain engineering, compression (decompressors/MISR), at-speed strategies, diagnosis, X-handling; additionally, integrate with synthesis/STA/DFM.
SoC, Access & Hierarchy
4) System-on-Chip Test Architectures: Nanometer DFT — Laung-Terng Wang, Charles E. Stroud, Nur A. Touba
Focus: core-based test in the many-IP world.
Takeaways: IEEE 1500 wrappers, TAM sizing/scheduling, hierarchical reuse, power-aware test, and LBIST/MBIST integration at scale; moreover, apply these to reduce bring-up time.
5) The Boundary-Scan Handbook (IEEE 1149.1/1149.x) — Kenneth M. Parker
Focus: access and bring-up that DFT must enable.
Takeaways: TAP, boundary-scan cells, interconnect test, programming flows, and how 1149.1/1149.6/1149.7 complement on-chip DFT; consequently, lab debug becomes more systematic.
6) IJTAG / IEEE 1687 Practitioner Guides — various authors
Focus: embedded instruments and scalable access networks.
Takeaways: ICL/PDL, instrument discovery/retargeting, and stitching 1687 with 1500/1149.1 for unified debug/monitoring; additionally, enable field diagnostics.
BIST & Memory Specialists
7) Built-In Test for VLSI: Pseudorandom Techniques — Bardell, McAnney, Savir
Focus: the math behind LBIST.
Takeaways: PRPG/MISR design, phase shifters, space/time compaction, aliasing analysis, and X-tolerant LBIST under functional clocks; moreover, justify choices with provable bounds.
8) Testing Semiconductor Memories: Theory & Practice — Ad J. van de Goor
Focus: industrial-strength MBIST & repair.
Takeaways: March families (C-, SS, RAW), NPSF/coupling/disturb models, retention/DRF, BIRA/BISR; furthermore, select algorithms with evidence, not folklore.
Additional Advanced Texts
9) Testing of Digital Systems — N. K. Jha, S. Gupta
Focus: optimization and delay/low-power detail.
Takeaways: power-aware scheduling, delay/path-delay test, test-synthesis links, and formulations to hit IR/thermal limits; consequently, coverage rises while power stays in check.
10) DFT/Diagnosis Compendia & Handbooks — edited volumes
Focus: topic-specific chapters from leading groups.
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