This course is designed to equip learners with core analog layout design skills essential for custom IC design.
It covers MOSFET layout techniques, matching principles, parasitic minimization, analog-specific DRC/LVS/ERC checks, and post-layout simulations.
You will gain hands-on experience using industry-standard EDA tools
(Cadence Virtuoso / Mentor Graphics / Synopsys Custom Compiler) and work on a complete analog IP layout as your capstone project.
Learning Outcomes
By the end of this course, learners will be able to:
- Understand layout fundamentals and their impact on analog circuit performance.
- Implement device matching and symmetry techniques for precision analog circuits.
- Perform layout vs. schematic (LVS) and design rule checks (DRC) for full-custom designs.
- Optimize layouts for low noise, low power, and high performance.
- Perform parasitic extraction (PEX) and post-layout simulation for verification.
- Deliver a tape-out ready analog layout.
Course Modules
Module 1: Introduction to Analog Layout
- Role of Layout in Analog IC Design
- Differences Between Digital & Analog Layout
- Overview of IC Fabrication Flow
- Introduction to PDKs and Design Rules
Lab: Explore PDK layers and technology files in Cadence Virtuoso
Module 2: CMOS Process & Device Layout Fundamentals
- CMOS Fabrication Steps (Overview)
- Active, Poly, Metal, and Via Layers
- Understanding Well Structures and Isolation Techniques
- Basic MOSFET Layout Structure
Lab: Create NMOS and PMOS layouts with DRC clean output
Module 3: Analog Layout Design Principles
- Matching Techniques: Common-Centroid, Interdigitation, Symmetry
- Guard Rings, Dummy Devices, and Isolation Strategies
- Orientation and Placement for Low Mismatch
Mini Project: Layout of Matched Current Mirror with Common-Centroid
Module 4: Parasitics in Analog Layout
- Sources of Parasitics: Capacitance, Resistance, Coupling
- Impact on Circuit Performance (Gain, Bandwidth, Offset)
- Parasitic Reduction Techniques in Layout
Lab: Extract and Analyze Parasitics for a Differential Pair
Module 5: Layout for Key Analog Building Blocks
- Differential Pair Layout
- Current Mirrors & Bias Circuits
- Operational Amplifiers (Op-Amps)
- Bandgap Reference Circuits
Lab: Layout of Differential Pair with Guard Ring and Shielding
Module 6: Floorplanning & Routing for Analog ICs
- Hierarchical Layout vs Flat Layout
- Power Routing and Ground Shielding
- Clock and Sensitive Signal Routing in Mixed-Signal Chips
Lab: Floorplan for 2-Stage Op-Amp Layout
Module 7: Design Rule Checks (DRC) & LVS
- Understanding DRC Rules (Width, Spacing, Enclosure, etc.)
- LVS Process & Common Errors
- ERC (Electrical Rule Check) Basics
Lab: Run DRC/LVS/ERC for a Current Mirror Layout
Module 8: Post-Layout Verification
- Parasitic Extraction (PEX)
- Post-Layout Simulation & Comparison with Pre-Layout Results
- Layout Optimization Based on PEX
Activity: Optimize Op-Amp Layout for Reduced Offset
Module 9: Advanced Analog Layout Topics
- Layout for Low-Noise Circuits
- High-Frequency Analog Layout Considerations
- ESD Protection in Analog Blocks
- Latch-Up Prevention Techniques
Lab: Layout of Low-Noise Amplifier with Shielded Routing
Module 10: Tape-Out Preparation
- Design Sign-Off Flow for Analog IP
- GDSII Generation and Verification
- Documentation & Handover Process
Workshop: Preparing a Tape-Out Package
Module 11: Tools & Scripting for Layout Automation
- Skill (Cadence) & Python Scripting Basics
- Automating Repetitive Layout Tasks
- Introduction to P Cell Design
Lab: Create a P Cell for Parameterized Resistor Layout
Module 12: Capstone Project
Project Options:
- Layout of an Operational Amplifier with Matching and Parasitic Optimization
- Layout of a Bandgap Reference Circuit
- Layout of a Sigma-Delta ADC Front-End Block
